8086 Microprocessor Architecture

The Intel 8086 Microprocessor was the first in the long line of “x86” processors. It was a 16-bit microprocessor and had significantly different architecture from the previous 8-bit 8085 Microprocessor. One of the first steps in learning about a Microprocessor is to understand its Architecture. You will get a clear idea about its internal logic configuration which will further help you in writing programs for the microprocessor. So, in this guide, let us take a quick and close look at the Intel 8086 Microprocessor Architecture.

What is a Microprocessor’s Architecture?

Before taking a look at the functional block diagram and the 8086 Microprocessor architecture, let me explain to you what exactly is a Microprocessor’s Architecture.

In simple words, the Architecture of a Microprocessor is nothing but its internal logic design (the circuit). Internally, a microprocessor consists of several logical circuits, flip-flops, registers and many more components.

Using these functional blocks, we use the microprocessor to manipulate the data and communicate (transfer data) with memory and IO devices with the help of programming. The architecture of the Microprocessor determines how this data manipulation and communications jobs are done.

Each generation of Microprocessors has a new and/or upgraded architecture that can add a significant performance improvement over the previous generation. For example, until the 8085 Microprocessor, Intel designed them as 8-bit Microprocessors. But starting with 8086, the architecture has been modified as 16-bit. This means that the Arithmetic Logic Unit (ALU) must be redesigned to work with 16-bit data and also the registers are now 16-bit wide.

Functional Block Diagram of a Microprocessor

Let us begin understanding the 8086 Microprocessor Architecture by starting with its functional block diagram. The following image shows a simplified version of the internal block diagram of the 8086 Microprocessor.

You can see that the block diagram is divided into two functional units known as Execution Unit (EU) and Bus Interface Unit (BIU). There is additionally a system clock that is responsible for providing the basic timing function and a control unit that is responsible for providing all the control signals (not shown in this block diagram).

The Intel 8086 Microprocessor Architecture

The highlight of 8086 Architecture was Parallel Processing or Pipeline Operation. To achieve this, Intel split the internal architecture of the microprocessor into two functional blocks, which are the Bus Interface Unit (BIU) and Execution Unit (EU).

• Bus Interface Unit (BIU) consists of the Adder (Address Generation Unit) for calculating the Address, 4 segment registers (16-bit), Instruction Pointer (16-bit), Instruction Queue (6 Byte long) and a Bus Control System.
• The Execution Unit (EU) on the other hand consists of the 16-bit Arithmetic Logic Unit (ALU), 8 general purpose registers (16-bit), a flag register (16-bit) and a Control Unit (CU).

BIU is responsible for handling all the data and address transfer on the bus. It calculates the addresses and using these addresses, it fetches the instructions from memory. It also reads and writes data from/to memory and IO Ports.

The EU, on the other hand, is responsible for instructing the BIU the location of data or instructions, decode and execute instructions.

These two blocks operate independently and also at the same time. Thus, making the “fetch” part of the instructions and the “execute” part of the instructions two separate operations and achieving “parallel processing”.

The result is an efficient use of the system bus and an improved performance of the 8086 Microprocessor.

Let us now explore the Architecture of the 8086 Microprocessor in detail. Before that, here is the image depicting a detailed layout of the 8086 Architecture.

Execution Unit (EU)

The Execution Unit (EU) is a part of the 8086 Microprocessor that contains all the digital logic circuits for executing the instructions. It contains the Arithmetic Logic Unit (ALU), Registers (General Purpose, Flag, Pointer, and Index), Instruction Decoder and Timing and Control Circuit.

The responsibilities of the EU include:

• Execute all Instructions
• Provide Address to Bus Interface Unit (BIU) to fetch data and/or instructions from Memory or IO Devices
• Manipulate Registers (General Purpose Registers and Flag Register)

Bus Interface Unit (BIU)

The Bus Interface Unit, as the name suggests, performs all the bus associated operations on behalf of the Execution Unit (EU). Upon receiving command from the EU, the BIU calculates the address and fetches instruction from memory at that address and places it in the ‘Instruction Queue.’ The Execution Unit will then take the instruction from this queue and start executing it.

BIU also reads/writes data from/to memory and IO Ports. So, it is clear that the Execution Unit doesn’t have direct access to the memory or IO Ports but it communicates with them only through BIU.

There are 5 registers associated with the BIU. They are the 4 Segment Registers and an Instruction Pointer. Apart from these registers, the BIU also has an address generation unit (which is basically an Adder) and a 6 Byte Instruction Queue.

When the bus is available i.e., if the EU doesn’t use it, then the BIU fetches the next instruction to be executed from the memory and sends it to the Instruction Queue.

Instruction Queue

The Instruction queue is a First-In-First-Out (FIFO) Queue i.e., the instruction that made a first entry to the queue will be the first one to be extracted and executed by the EU. In this way, the execution of instructions will speed up as the instruction is readily available right in the Microprocessor rather than waiting for it to be fetched from memory.

This concept of prefetching the instructions is a design strategy of Pipelining (sometimes also known as Parallel Processing), where the Fetching and Executing of instructions can happen at the same time as they are handled by two separate entities.

An important point about this instruction queue is that it works normally until a branch instruction comes up. In the event of a branch instruction, the instruction to be executed will be a new instruction rather than the one in the queue. Hence, the BIU will reset the queue (flushes the contents of the queue), fetch the instruction from a new address and start filling the queue from this new address location.

Register Set of 8086 Microprocessor

All microprocessors have internal registers, which is nothing but a type of on-chip RAM. There are two types of registers: General Purpose Registers and Special Purpose (or Function) Registers. 

General Purpose Registers act as temporary storage that hold the operands (data or value) of arithmetic or logical operations. Special Function Registers, on the other hand, control the operations of a microprocessor. 

Coming to the 8086 Microprocessor, it has 14 16-bit registers. Of these, the Execution Unit has 9 Registers, while the remaining 5 are a part of the Bus Interface Unit.

The following image shows the Register Model of the 8086 CPU.

General Purpose Data Registers

The 808 Microprocessor has four data registers:

• AX
• BX
• CX
• DX

While they are 16-bit registers, you can address them by their upper and lower bytes (essentially two separate 8-bit registers, each). The low byte has a name RL while the higher byte has RH. Here, R can be A, B, C, or D.

• AX – AH and AL
• BX – BH and BL
• CX – CH and CL
• DX – DH and DL

These four registers are the main data registers of the 8086 CPU that store temporary data. Hence, we sometimes call them Scratchpad Registers. In addition to being general purpose data registers, these four registers also have some special uses. Let us take a look at that.

AX

This is the main Accumulator register. For 16-bit operations, AX acts as the accumulator while AL is the accumulator for 8-bit operations. The accumulator register is an important part of division, multiplication, shift, rotate, string, and IO operations.

Generally speaking, the accumulator register has somewhat less importance in 8086 Microprocessors than in 8085 Microprocessors. In an 8085 Microprocessor, it is almost a guarantee that one of two operands will be in the accumulator. Apart from some special instructions, you have to explicitly mention the source and destination registers in case of 8086 Microprocessor.

Note that the ‘destination’ register (or a memory location) is where the microprocessor puts the output/result of an operation.

BX, CX, and DX

BX is the Base Register. It acts as a pointer for the offset of the data segment.

CX (or CL) is the Count Register. It acts as a Counter in string manipulation instructions as well as loop, shift, and rotate instructions. In loop instructions for example, CX (or CL) holds the value of number of repetitions and it automatically decreases after every iteration. When the value of CX becomes zero, the execution of loop instruction is terminated.

DX is the Data Register and is a primary part of DIV and MUL instructions. When DIV instruction comes up, the DX Register holds the higher word of the 32-bit operand. After the division operation, it holds the remainder. In MUL instruction, DX holds the higher word of the 32-bit result.

Pointer and Index Registers

The 8086 Microprocessor has two Pointer Registers (Stack Pointer SP and Base Pointer BP) and two Index Registers (Source Index SI and Destination Index DI). All the four registers are 16-bit only (no 8-bit lower/higher bytes).

• The Stack Pointer (SP) holds the address of the top of the Program Stack (a special location in memory that is accessed by instructions such as PUSH, POP, CALL, etc.).
• Base Pointer (BP) provides indirect access to data in Stack Memory i.e., it can hold the address of data in the Stack.
• The main purpose of Source Index (SI) and Destination Index (DI) is to hold addresses in various addressing modes (Indexed, Base Indexed, and Relative Base Indexed). In string manipulation instructions, SI and DI hold the source and destination addresses respectively.

Apart from the Stack Pointer (SP), the remaining three registers (BP, SI, and DI) can also act as general data storage registers.

Segment Registers

Memory Segmentation is an important part of the 8086 Microprocessor. We will understand Memory Segmentation in the 8086 CPU is a separate section. For the time being, remember that with memory segmentation, the 8086 Microprocessor can access more physical data than it is capable of. This is possible by dividing the memory into multiple smaller segments.

The Segment Registers hold the address of corresponding segments.

• Code Segment (CS) Register for Code Segment
• Data Segment (DS) Register for Data Segment
• Stack Segment (SS) Register for Stack Segment
• Extra Segment (ES) Register for Extra Segment

These registers, along with pointer and index registers, are used to generate the 20-bit Physical Address to access 1 MB Memory. We will learn how this works in the next section.

Instruction Pointer

The Instruction Pointer (IP) is also known as Program Counter (PC). It holds the address (in the Code Segment) of the next instruction that has to be executed by the processor. The combination of Code Segment Register (CS) and Instruction Pointer (IP) generates the 20-bit address for the next instruction.

Flag Register

The Flag register is also known as Processor Status Word (PSW). It is a 16-bit register and out of those 16-bits only 9 are used while the remaining 7 are unused.

In those 9 bits, 6 bits are used as Conditional (or Status) Flags and the remaining 3 are Control Flags. Internally, the 16 bits of the Flag Register are nothing but 16 independent flip-flops.

• The conditional Flag Bits are: Carry, Parity, Auxiliary Carry, Zero Sign, and Overflow. These bits are set or reset depending on the results of an arithmetic or logical operation.
• The Control Flag Bits are: Trap, Interrupt, and Direction. We have to set or reset these three flags depending on the operation.

Conditional (Status) Flags

Let us understand the importance of each and every flag in the Flag register.

• Carry Flag (CF): This flag is set when there is a carry out of the most significant bit (MSB) during addition (or borrow in case of subtraction).
• Parity Flag (PF): This flag is set if the result of an 8-bit operation (or lower byte in case of 16-bit operation) has an even number of 1s.
• Auxiliary Carry Flag (AF): It is set if there is a carry from lower nibble to higher nibble of an 8-bit data (or the lower order byte in case of a 16-bit data).
• Zero Flag (ZF): It is set if the result of an operation (arithmetic or logical) is zero.
• Sign Flag (SF): If the result of an arithmetic or logical operation is a negative number, then the Sign Flag (SF) is set. If the MSB of the result is 1 (indicating that the number is negative), then the Sign Flag is set.
• Overflow Flag (OF): This flag is set if the result of an arithmetic operation overflows i.e., the size of the result exceeds the capacity of the destination register/memory location.

Control Flags

• Trap (or Trace) Flag (TF): Set this flag (through software) to put the processor in single step (step-by-step) mode during debugging. The processor generates an internal interrupt after execution of each instruction. 
• Interrupt Flag (IF): Set this flag if you want the processor to recognize the external maskable interrupts.
• Direction Flag (DF): This flag is used in string manipulation operations. If set, the processor will process the strings from right to left (auto decrement mode). If this flag is cleared, strings are processed from left to right (auto increment mode).

Memory Segmentation

Let us quickly understand the concept of memory segmentation implemented in 8086 microprocessors. From the previous guide, you might be familiar that the 8086 Microprocessor has a 20-bit Address Bus.

With this 20-bit bus, it can access up to 2²⁰ bytes (1,048,576 Bytes or 1 Megabyte) of physical memory with addresses ranging from 00000H – FFFFFH. If all the registers are 16-bit wide and the ALU is also 16-bit, then how does the microprocessor generate a 20-bit address?

Here comes the concept of Memory Segmentation. In this, the 1 MB of Physical Memory is logically divided into several Segments (16 to be specific) each with a size of 64 KB.

The addresses of these 16 segments are assigned from 0000H to F0000H. The offset addresses range from 0000H to FFFFH. When you add the segment address (after shifting it to left by 4-bits) and the offset address, you will get the 20-bit physical address.

We can get the Segment Address by accessing the respective Segment Register, depending on the type of value we want to access (Code, Stack, Data, etc.).

The 20-bit physical address is generally represented as Base Address:Offset. Here, the base address is nothing but the starting address of a segment.

For example, assume we want to get the byte located in the Data Segment with a logical address of 2222H:0069H. This means, the Data Segment (DS) register will contain 2222H. Here’s how we calculate the physical address

• Segment Address = 2222H
• Segment Address Left Shift by 4-bits = 22220H
• Add Offset to this = 22289H

So, the Physical Address will be 22289H.

Segment Registers and Offset Registers

The following table shows the common combination of segment registers and possible offset registers.

Conclusion

This was a brief overview of the 8086 Microprocessor Architecture. We learned about all the functional blocks of the 8086 CPU including the Execution Unit (EU), Bus Interface Unit (BIU), all the registers, and even a basic understanding of the Memory Segmentation.

In the upcoming guides, we will further explore the ‘memory’ part of the 8086 Microprocessor. If you have any queries, requests, or comments, do let me know in the comments section.